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1 mx25U6435F datasheet rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
2 contents 1. features .............................................................................................................................................................. 4 2. general description ..................................................................................................................................... 6 table 1. additional feature .......................................................................................................................... 7 3. pin configurations ......................................................................................................................................... 8 4. pin description .................................................................................................................................................. 8 5. block diagram ................................................................................................................................................... 9 6. data protection .............................................................................................................................................. 10 table 2. protected area sizes ....................... ............................................................................................ 11 table 3. 4k-bit secured otp defnition ....................... ............................................................................. 12 7. memory organization ................................................................................................................................... 13 table 4. memory organization .................................................................................................................. 13 8. device operation ............................................................................................................................................ 14 8-1. quad peripheral interface (qpi) read mode .......................................................................................... 16 9. command description ................................................................................................................................... 17 table 5. command set .............................................................................................................................. 17 9-1. w rite enable (wren) ... ........................................................................................................................... 21 9-2. w rite disable (wrdi) ............................................................................................................................... 22 9-3. read identifcation (rdid) ... .................................................................................................................... 23 9-4. release from deep power-down (rdp), read electronic signature (res) ... ........................................ 24 9-5. read electronic manufacturer id & device id (rems) ........................................................................... 26 9-6. qpi id read (qpiid) ............................................................................................................................... 27 table 6. id defnitions .............................................................................................................................. 27 9-7. read status register (rdsr) ................................................................................................................. 28 9-8. w rite status register (wrsr) ................................................................................................................. 32 table 7. protection modes ......................................................................................................................... 33 9-9. read data bytes (read) ... ..................................................................................................................... 36 9-10. read data bytes at higher speed (f ast_read) ... ............................................................................... 37 9-11. dual read mode (dread) ...................................................................................................................... 39 9-12. 2 x i/o read mode (2read) ................................................................................................................... 40 9-13. quad read mode (qread) ... ................................................................................................................. 41 9-14. 4 x i/o read mode (4read) ................................................................................................................... 42 9-15. burst read ... ............................................................................................................................................ 45 9-16. performance enhance mode ................................................................................................................... 46 9-17. performance enhance mode reset ......................................................................................................... 49 9-18. sector erase (se) .................................................................................................................................... 50 9-19. block erase (be32k) ............................................................................................................................... 51 9-20. block erase (be) ..................................................................................................................................... 52 9-21. chip erase (ce) ....................................................................................................................................... 53 9-22. page program (pp) ................................................................................................................................. 54 9-23. 4 x i/o page program (4pp) ... ................................................................................................................. 56 9-24. deep power-down (dp) ........................................................................................................................... 57 9-25. enter secured otp (enso) .................................................................................................................... 58 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
3 9-26. exit secured otp (exso) ... .................................................................................................................... 58 9-27. read security register (rdscur) ......................................................................................................... 58 table 8. security register defnition ......................................................................................................... 59 9-28. w rite security register (wrscur) ......................................................................................................... 59 9-29. w rite protection selection (wpsel) ........................................................................................................ 60 9-30. single block lock/unlock protection (sblk/sbulk) .............................................................................. 63 9-31. read block lock status (rdblock) ...................................................................................................... 65 9-32. gang block lock/unlock (gblk/gbulk) ............................................................................................... 65 9-33. program/ erase suspend/ resume ......................................................................................................... 66 9-34. erase suspend ........................................................................................................................................ 66 9-35. program suspend .................................................................................................................................... 66 9-36. write-resume ... ....................................................................................................................................... 68 9-37. no operation (nop) ................................................................................................................................ 68 9-38. software reset (reset-enable (rsten) and reset (rst)) ................................................................... 68 9-39. read sfdp mode (rdsfdp) .................................................................................................................. 70 table 9. signature and parameter identifcation data values .................................................................. 71 table 10. parameter table (0): jedec flash parameter tables .............................................................. 72 table 11. parameter table (1): macronix flash parameter tables ............................................................ 74 10. reset .................................................................................................................................................................. 76 table 12. reset timing .............................................................................................................................. 76 11. power-on state ............................................................................................................................................. 77 12. electrical specifications ........................................................................................................................ 78 table 13. absolute maximum ratings ....................... ................................................................................ 78 table 14. capacitance ............................................................................................................................... 78 table 15. dc characteristics ..................................................................................................................... 80 table 16. ac characteristics ....................... ............................................................................................. 81 13. operating conditions ................................................................................................................................. 83 table 17. power-up timing and vwi threshold ....................................................................................... 85 13-1. initial delivery state ................................................................................................................................. 85 14. erase and programming performance .............................................................................................. 86 15. latch-up characteristics ........................................................................................................................ 86 16. ordering information ................................................................................................................................ 87 17. part name description ............................................................................................................................... 88 18. package information .................................................................................................................................. 89 19. revision history ........................................................................................................................................... 91 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
4 1. features 1.8v 64m-bit [x 1/x 2/x 4] cmos mxsmio ? (serial multi i/o) flash memory general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 67,108,864 x 1 bit structure or 33,554,432 x 2 bits (two i/o mode) structure or 16,777,216 x 4 bits (four i/o mode) structure ? equal sectors with 4k byte each, or equal blocks with 32k byte each or equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 1.65 to 2.0 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v ? low vcc write inhibit is from 1.0v to 1.4v performance ? high performance - fast read for spi mode - 1 i/o: 104mhz with 8 dummy cycles - 2 i/o: 84mhz with 4 dummy cycles, equivalent to 168mhz - 4 i/o: 104mhz with 2+4 dummy cycles, equivalent to 416mhz - fast read for qpi mode - 4 i/o: 84mhz with 2+2 dummy cycles, equivalent to 336mhz - 4 i/o: 104mhz with 2+4 dummy cycles, equivalent to 416mhz - fast program time: 0.5ms(typ.) and 3ms(max.)/page (256-byte per page) - byte program time: 12us (typical) - 8/16/32/64 byte w rap-around burst read mode - fast erase time: 35ms (typ.)/sector (4k-byte per sector); 200ms(typ.)/block (32k-byte per block), 350ms(typ.) / block (64k-byte per block) ? low power consumption - low active read current: 20ma(typ.) at 104mhz, 15ma(typ.) at 84mhz - low active erase current: 18ma (typ.) at sector erase, block erase (32kb/64kb); 20ma at chip erase - low active programming current: 20ma (typ.) - standby current: 15ua (typ.) ? deep power down: 1.5ua(typ.) ? t ypical 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? advanced security features - block lock protection the bp0-bp3 status bit defnes the size of the area to be software protection against program and erase instruc - tions - additional 4k-bit secured otp for unique identifer ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector or block - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
5 ? status register feature ? command reset ? program/erase suspend ? electronic identifcation - jedec 1-byte manufacturer id and 2-byte device id - res command for 1-byte device id - rems command for 1-byte manufacturer id and 1-byte device id ? support serial flash discoverable parameters (sfdp) mode hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? so/sio1 - serial data output or serial data input/output for 2 x i/o read mode and 4 x i/o read mode ? wp#/sio2 - hardware write protection or serial data input/output for 4 x i/o read mode ? reset#/sio3 - hardware reset pin or serial input & output for 4 x i/o read mode ? p ackage -8-pin sop (200mil) -8-land wson (6x5mm) - all devices are rohs compliant and halogen-free rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
6 2. general description mx25U6435F is 64mb bits serial flash memory, which is confgured as 8,388,608 x 8 internally. when it is in two or four i/o mode, the structure becomes 33,554,432 bits x 2 or 16,777,216 bits x 4. mx25U6435F feature a serial pe - ripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single i/o mode. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. when it is in two i/o read mode, the si pin and so pin become sio0 pin and sio1 pin for address/dummy bits in - put and data output. when it is in four i/o read mode, the si pin, so pin, wp# pin and reset# pin become sio0 pin, sio1 pin, sio2 pin and sio3 pin for address/dummy bits input and data output. the mx25U6435F mxsmio ? (serial multi i/o) provides sequential read operation on whole chip. after program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specifed page or sector/block locations will be executed. progr am command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4k-byte), block (32k-byte), or block (64k-byte), or whole chip basis. to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. advanced security features enhance the protection and security functions, please see security features section for more details. when the device is not in operation and cs# is high, it is put in standby mode and draws less than 30ua dc cur - rent. the mx25U6435F utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
7 table 1. additional feature protection and security mx25U6435F flexible block protection (bp0-bp3) v 4k-bit security otp v read performance mx25U6435F i/o mode spi qpi i/o 1 i/o 1i /2o 2 i/o 1i/4o 4 i/o 4 i/o 4 i/o 4 i/o dummy cycle 8 8 4 8 4 6 4 6 frequency 104mhz 104mhz 84 mhz 104mhz 84 mhz 104mhz 84 mhz 104mhz rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
8 3. pin configurations 4. pin description symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for 2xi/o or 4xi/ o read mode) sclk clock input wp#/sio2 write protection: connect to gnd or serial data input & output (for 4xi/o read mode) reset#/sio3 hardware reset pin active low or serial data input & output (for 4xi/o read mode) vcc + 1.8v power supply gnd ground 8-land wson (6x5mm) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd 8 7 6 5 vcc reset#/sio3 sclk si/sio0 8-pin sop (200mil) 1 2 3 4 cs# so/sio1 wp#/sio2 gnd vcc reset#/sio3 sclk si/sio0 8 7 6 5 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
9 5. block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk so/sio1 clock generator state machine mode logic sense amplifier hv generator output buffer cs# wp#/sio2 reset#/sio3 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
10 6. data protection during power transition, there may be some false system level signals which result in inadvertent erasure or pro - gramming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command se - quences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? power-on reset: to avoid sudden power switch by system power supply transition, the power-on reset may pro - tect the flash. ? valid command length checking: the command length will be checked whether it is at byte base and completed on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before is - suing other commands to change data. ? deep power down mode: by entering deep power down mode, the fash device is under protected from writing all commands except release from deep power down mode command (rdp) and read electronic signature command (res) and softreset command. ? advanced security features: there are some protection and security features which protect content from inad - vertent write and hostile access. i. block lock protection - the software protected mode (spm) use (bp3, bp2, bp1, bp0) bits to allow part of memory to be protected as read only. the protected area defnition is shown as "table 2. protected area sizes" , the protected areas are more fexible which may protect various area by setting value of bp0-bp3 bits. - the hardware proteced mode (hpm) use wp#/sio2 to protect the (b p3, bp2, bp1, bp0) bits and status reg - ister write protect bit. - in f our i/o and qpi mode, the feature of hpm will be disabled. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
11 table 2. protected area sizes status bit protect level bp3 bp2 bp1 bp0 0 0 0 0 0 (none) 0 0 0 1 1 (1 block, protected block 127th) 0 0 1 0 2 (2 blocks, protected block 126th~127th) 0 0 1 1 3 (4 blocks, protected block 124th~127th) 0 1 0 0 4 (8 blocks, protected block 120th~127th) 0 1 0 1 5 (16 blocks, protected block 112nd~127th) 0 1 1 0 6 (32 blocks, protected block 96th~127th) 0 1 1 1 7 (64 blocks, protected block 64th~127th) 1 0 0 0 8 (64 blocks, protected block 0th~63th) 1 0 0 1 9 (96 blocks, protected block 0th~95th) 1 0 1 0 10 (112 blocks, protected block 0th~111st) 1 0 1 1 11 (120 blocks, protected block 0th~119th) 1 1 0 0 12 (124 blocks, protected block 0th~123rd) 1 1 0 1 13 (126 blocks, protected block 0th~125th) 1 1 1 0 14 (127 blocks, protected block 0th~126th) 1 1 1 1 15 (128 blocks, protected all) rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
12 ii. additional 4k-bit secured otp for unique identifer: to provide 4k-bit one-time program area for setting de - vice unique serial number - which may be set by factory or system customer . - security register bit 0 ind icates whether the chip is locked by factory or not. - to program the 4k-bit secured otp by entering 4k-bit secured otp mode (with enter security otp command), and going through normal program procedure, and then exiting 4k-bit secured otp mode by writing exit security otp command. - customer may lock-down the customer lockable secured otp by writing wrscur(write security register) com - mand to set customer lock-down bit1 as "1". please refer to "table 8. security register defnition" for security register bit defnition and "table 3. 4k-bit secured otp defnition" for address range defnition. - note: once lock-down whatever by factory or customer , it cannot be changed any more. while in 4k-bit secured otp mode, array access is not allowed. table 3. .elw6hfxuhg273hqlwlrq address range size standard factory lock customer lock xxx000~xxx00f 128-bit esn (electrical serial number) determined by customer xxx010~xxx1ff 3968-bit n/a rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
13 table 4. memory organization 7. memory organization block(32k-byte) sector (4k-byte) 2047 7ff000h 7fffffh ? 2040 7f8000h 7f8fffh 2039 7f7000h 7f7fffh ? 2032 7f0000h 7f0fffh 2031 7ef000h 7effffh ? 2024 7e8000h 7e8fffh 2023 7e7000h 7e7fffh ? 2016 7e0000h 7e0fffh 2015 7df000h 7dffffh ? 2008 7d8000h 7d8fffh 2007 7d7000h 7d7fffh ? 2000 7d0000h 7d0fffh 47 02f000h 02ffffh ? 40 028000h 028fffh 39 027000h 027fffh ? 32 020000h 020fffh 31 01f000h 01ffffh ? 24 018000h 018fffh 23 017000h 017fffh ? 16 010000h 010fffh 15 00f000h 00ffffh ? 8 008000h 008fffh 7 007000h 007fffh ? 0 000000h 000fffh 252 251 250 address range 255 254 253 block(64k-byte) 125 2 1 0 127 126 0 5 4 3 2 1 individual block lock/unlock unit:64k-byte individual block lock/unlock unit:64k-byte individual block lock/unlock unit:64k-byte individual 16 sectors lock/unlock unit:4k-byte individual 16 sectors lock/unlock unit:4k-byte rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
14 8. device operation 1. before a command is issued, status register should be checked to ensure device is ready for the intended op - eration. 2. when incorrect command is inputted to this device, it enters standby mode and remains in standby mode until next cs# falling edge. in standby mode, so pin of the device is high-z. 3. when correct command is inputted to this device, it enters active mode and remains in active mode until next cs# rising edge. 4. input data is latched on the rising edge of serial clock (sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as "serial modes supported". 5. for the following instruct ions: rdid, rdsr, rdscur, read, fast_read, dread, 2read, 4read, qread, w4read, rdsfdp, res, rems, qpiid, rdblock, the shifted-in instruction sequence is followed by a data- out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be32k, be, ce, pp, 4pp, dp, enso, exso, wrscur, wpsel, sblk, sbulk, gbulk, suspend, resume, nop, rsten, rst, eqio, rstqio the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. while a w rite status register, program or erase operation is in progress, access to the memory array is ne - glected and will not affect the current operation of write status register, program, erase. figure 1. serial modes supported note: cpol indicates clock polarity of serial master, cpol=1 for sclk high while idle, cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
15 figure 2. serial input timing figure 3. output timing sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqx tclqv sclk so cs# si rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
16 8-1. quad peripheral interface (qpi) read mode qpi protocol enables user to take full advantage of quad i/o serial flash by providing the quad i/o interface in command cycles, address cycles and as well as data output cycles. enable qpi mode by issuing 35h command, the qpi mode is enabled. figure 4. enable qpi sequence (command 35h) mode 3 sclk sio0 cs# mode 0 234567 35 sio[3:1] 0 1 reset qpi (rstqio) to reset the qpi mode, the rstqio (f5h) command is required. after the rstqio command is issued, the device returns from qpi mode (4 i/o interface in command cycles) to spi mode (1 i/o interface in command cycles). note: for eqio and rstqio commands, cs# high width has to follow "write spec" tshsl for next instruction. figure 5. reset qpi mode (command f5h) sclk sio[3:0] cs# f5 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
17 9. command description table 5. command set read/write array commands mode spi spi/qpi spi spi spi/qpi spi command (byte) read (normal read) fast read (fast read data) dread (1i / 2o read command) 2read (2 x i/o read command) note1 4read (4 x i/o read) w4read 1st byte 03 (hex) 0b (hex) 3b (hex) bb (hex) eb (hex) e7 (hex) 2nd byte add1(8) add1(8) add1(8) add1(4) add1(2) add1 3rd byte add2(8) add2(8) add2(8) add2(4) add2(2) add2 4th byte add3(8) add3(8) add3(8) add3(4) add3(2) add3 5th byte dummy(8)/(4)* dummy(8) dummy(4) dummy(6) dummy(4) action n bytes read out until cs# goes high n bytes read out until cs# goes high n bytes read out by dual output until cs# goes high n bytes read out by 2 x i/o until cs# goes high quad i/o read with 6 dummy cycles quad i/o read for with 4 dummy cycles mode spi spi/qpi spi spi/qpi spi/qpi spi/qpi command (byte) qread (1i/4o read) pp (page program) 4pp (quad page program) se (sector erase) be 32k (block erase 32kb) be (block erase 64kb) 1st byte 6b (hex) 02 (hex) 38 (hex) 20 (hex) 52 (hex) d8 (hex) 2nd byte add1(8) add1 add1 add1 add1 add1 3rd byte add2(8) add2 add2 add2 add2 add2 4th byte add3(8) add3 add3 add3 add3 add3 5th byte dummy(8) action n bytes read out by quad output until cs# goes high to program the selected page quad input to program the selected page to erase the selected sector to erase the selected 32k block to erase the selected block * the fast read command (0bh) when under qpi mode, the dummy cycle is 4 clocks. mode spi/qpi command (byte) ce (chip erase) 1st byte 60 or c7 (hex) 2nd byte 3rd byte 4th byte 5th byte action to erase whole chip rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
18 register/setting commands command (byte) wren (write enable) wrdi (write disable) rdsr (read status register) wrsr (write status register) wpsel (write protect selection) eqio (enable qpi) mode spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi spi 1st byte 06 (hex) 04 (hex) 05 (hex) 01 (hex) 68 (hex) 35 (hex) 2nd byte values 3rd byte 4th byte 5th byte action sets the (wel) write enable latch bit resets the (wel) write enable latch bit to read out the values of the status register to write new values of the status register to enter and enable individal block protect mode entering the qpi mode command (byte) rstqio (reset qpi) pgm/ers suspend (suspends program/erase) pgm/ers resume (resumes program/erase) dp (deep power down) rdp (release from deep power down) sbl (set burst length) mode qpi spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi 1st byte f5 (hex) b0 (hex) 30 (hex) b9 (hex) ab (hex) c0 (hex) 2nd byte value 3rd byte 4th byte 5th byte action exiting the qpi mode enters deep power down mode release from deep power down mode to set burst length rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
19 command (byte) rdid (read identifc- ation) res (read electronic id) rems (read electronic manufacturer & device id) qpiid (qpi id read) rdsfdp enso (enter secured otp) exso (exit secured otp) mode spi spi/qpi spi qpi spi/qpi spi/qpi spi/qpi 1st byte 9f (hex) ab (hex) 90 (hex) af (hex) 5a (hex) b1 (hex) c1 (hex) 2nd byte x x add1(8) 3rd byte x x add2(8) 4th byte x add (note 2) add3(8) 5th byte dummy(8) action outputs jedec id: 1-byte manufacturer id & 2-byte device id to read out 1-byte device id output the manufacturer id & device id id in qpi interface read sfdp mode to enter the 4k-bit secured otp mode to exit the 4k- bit secured otp mode command (byte) rdscur (read security register) wrscur (write security register) sblk (single block lock sbulk (single block unlock) rdblock (block protect read) gblk (gang block lock) gbulk (gang block unlock) mode spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi spi/qpi 1st byte 2b (hex) 2f (hex) 36 (hex) 39 (hex) 3c (hex) 7e (hex) 98 (hex) 2nd byte add1 add1 add1 3rd byte add2 add2 add2 4th byte add3 add3 add3 5th byte action to read value of security register to set the lock- down bit as "1" (once lock- down, cannot be update) individual block (64k- byte) or sector (4k-byte) write protect individual block (64k-byte) or sector (4k- byte) unprotect read individual block or sector write protect status whole chip write protect whole chip unprotect id/security commands rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
20 note 1: the count base is 4-bit for add(2) and dummy(2) because of 2 x i/o. and the msb is on so/sio1 which is different from 1 x i/o condition. note 2: add=00h will output the manufacturer id frst and add=01h will output device id frst. note 3: it is not recommended to adopt any other code not in the command defnition table, which will potentially enter the hid - den mode. note 4: before executing rst command, rsten command must be executed. if there is any other command to interfere, the reset operation will be disabled. note 5: the number in parentheses after "add" or "data" stands for how many clock cycles it has. for example, "data(8)" represents there are 8 clock cycles for the data in. reset commands command (byte) nop (no operation) rsten (reset enable) rst (reset memory) release read enhanced mode spi/qpi spi/qpi spi/qpi spi/qpi 1st byte 00 (hex) 66 (hex) 99 (hex) ff (hex) 2nd byte 3rd byte 4th byte 5th byte action (note 4) all these commands ffh, 00h, aah or 55h will escape the performance mode rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
21 9-1. write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, 4pp, se, be32k, be, ce, and wrsr, which are intended to change the device content wel bit should be set every time after the wren instruction setting the wel bit. the sequence of issuing wren instruction is: cs# goes lowsending wren instruction code cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. figure 6. write enable (wren) sequence (spi mode) 21 34567 high-z 0 06h command sclk si cs# so mode 3 mode 0 figure 7. write enable (wren) sequence (qpi mode) sclk sio[3:0] cs# 06h 0 1 command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
22 9-2. write disable (wrdi) the write disable (wrdi) instruction is to reset write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes lowsending wrdi instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the wel bit is reset by following situations: - power-up - reset# pin driven low - completion of w rite disable (wrdi) instruction - completion of w rite status register (wrsr) instruction - completion of page program (pp) instruction - completion of quad page program (4pp) instruction - completion of sector erase (se) instruction - completion of block erase 32kb (be32k) instruction - completion of block erase (be) instruction - completion of chip erase (ce) instruction - program/erase suspend - completion of softreset command - completion of w rite security register (wrscur) command - completion of w rite protection selection (wpsel) command figure 8. write disable (wrdi) sequence (spi mode) 21 34567 high-z 0 mode 3 mode 0 04h command sclk si cs# so figure 9. write disable (wrdi) sequence (qpi mode) sclk sio[3:0] cs# 04h 0 1 command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
23 9-3. read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macro - nix manufacturer id and device id are listed as "table 6. id defnitions" . 7khhtxhqfhrilxlqj5','lqwuxfwlrql&6jrhor:hqglqj5','lqwuxfwlrqfrgh:elw,'gdwdrxw rq62:wrhqg5','rshudwlrqfdqgulyh&6wrkljkdwdqwlphgxulqjgdwdrxw while program/erase operation is in progress, it will not decode the rdid instruction, therefore there's no effect on wkhffohrisurjudphudhrshudwlrqklfklfxuuhqwolqsurjuh:khq&6jrhkljkwkhghylfhldwwdqge stage. figure 10. read identifcation (rdid) sequence (spi mode only) 21 345678 9 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9fh mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
24 9-4. release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in "table 16. ac characteristics" . once in the stand- by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the rdp instruction is only for releasing from deep power down mode. reset# pin goes low will release the flash from deep power down mode. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as "table 6. id defnitions" . this is not the same as rdid instruction. it is not recommended to use for new design. for new de - sign, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/write cycle in progress. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be receive, decode, and execute instruction. figure 11. read electronic signature (res) sequence (spi mode) 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 2 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so abh command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
25 sclk sio[3:0] cs# mode 0 mode 3 msb lsb data out data in h0xxxxxx l0 deep power-down mode stand-by mode 0 abh 1 2 3 4 6 7 5 3 dummy bytes command figure 12. read electronic signature (res) sequence (qpi mode) figure 13. release from deep power-down (rdp) sequence (spi mode) 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so abh command mode 3 mode 0 figure 14. release from deep power-down (rdp) sequence (qpi mode) sclk sio[3:0] cs# abh 0 1 t res1 deep power-down mode stand-by mode command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
26 9-5. read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initi - ated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad - dress (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst. the device id values are listed in "table 6. id defnitions" . if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. (2) instruction is either 90(hex). figure 15. read electronic manufacturer & device id (rems) sequence (spi mode only) 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so 90h high-z command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
27 9-6. qpi id read (qpiid) user can execute this qpiid read instruction to identify the device id and manufacturer id. the sequence of issue qpiid instruction is cs# goes lowsending qpi id instructiondata out on socs# goes high. most signifcant bit (msb) frst. after the command cycle, the device will immediately output data on the falling edge of sclk. the manufacturer id, memory type, and device id data byte will be output continuously , until the cs# goes high. table 6. id defnitions command type command mx25U6435F rdid / qpiid 9fh / afh manufactory id memory type memory density c2 25 37 res abh electronic id 37 rems 90h manufactory id device id c2 37 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
28 9-7. read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition). it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes low sending rdsr instruction code status register data out on so. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. figure 16. read status register (rdsr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05h mode 3 mode 0 figure 17. read status register (rdsr) sequence (qpi mode) 0 1 3 sclk si o[3:0] cs# 05h 2 h0 l0 msb lsb 4 5 7 h0 l0 6 h0 l0 8 n h0 l0 sta tus byte status byte status byte status byte mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
29 wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command read array data (same add ress of pgm/ers) program /er ase su ccessfully yes yes program /erase fail no start verify ok? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel=1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdblock to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data figure 18. program/erase fow with read array data for user to check if program/erase operation is fnished or not, rdsr instruction fow are shown as follows: rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
30 figure 19. program/erase fow without read array data (read p_fail/e_fail fag) wr en co mm and program /erase co mm and write progr am data/address (w ri te erase address) rdsr command rdscur command program /er ase su ccessfully yes no program /erase fail yes start p_fail/e_fail =1 ? wip=0? progr am /e rase anot her bl ock? prog ram /er ase comp let ed no yes no rds r command* yes wel =1? no * issue rdsr to check bp[3:0]. * if wpsel = 1, issue rdblock to ch eck the block stat us. rdsr command read w el=0, bp[3:0] , q e, and srwd data rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
31 status register note 1: see the "table 2. protected area sizes" . bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) qe (quad enable) bp3 (level of protected block) bp2 (level of protected block) bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable 1=quad enable 0=not quad enable (note 1) (note 1) (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit status register the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write sta - tus register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the device will not accept program/erase/write status register instruction. the program/erase command will be ignored if it is ap - plied to a protected memory area. to ensure both wip bit & wel bit are both set to 0 and available for next program/ erase/operations, wip bit needs to be confrm to be 0 before polling wel bit. after wip bit confrmed, wel bit needs to be confrmed as 0. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in "table 2. protected area sizes" ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp3, bp2, bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase 32kb (be32k), block erase (be) and chip erase (ce) instructions (only if block protect bits (bp3:bp0) set to 0, the ce instruction can be executed). the bp3, bp2, bp1, bp0 bits are "0" as default, which is un- protected. qe bit. the quad enable (qe) bit, non-volatile bit, while it is "0" (factory default), it performs non-quad and wp#, reset# are enable. while qe is "1", it performs quad i/o mode and wp#, reset# are disabled. in the other word, if the system goes into four i/o mode (qe=1), the feature of hpm and reset will be disabled. srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protection (wp#/sio2) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp#/sio2 pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp3, bp2, bp1, bp0) are read only. the srwd bit defaults to be "0". rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
32 9-8. write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp3, bp2, bp1, bp0) bits to defne the pro - tected area of memory (as shown in "table 2. protected area sizes" ). the wrsr also can set or reset the quad enable (qe) bit and set or reset the status register write disable (srwd) bit in accordance with write protection (wp#/ sio2) pin signal, but has no effect on bit1(wel) and bit0 (wip) of the status register. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on sics# goes high. the cs# must go high exactly at the 8 bites or 16 bits data boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. note : the cs# must go high exactly at 8 bits or 16 bits data boundary to completed the write register command. figure 20. write status register (wrsr) sequence (spi mode) 21 345678 9 10 11 12 13 14 15 status register in 0 msb sclk si cs# so 01h high-z command mode 3 mode 0 7 6 5 4 3 2 1 0 figure 21. write status register (wrsr) sequence (qpi mode) sclk sio[3:0] cs# 2 3 10 h0 l0 command sr in mode 3 mode 3 mode 0 mode 0 01h rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
33 software protected mode (spm): - when srwd bit=0, no matter wp#/sio2 is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software protected mode (spm). - when srwd bit=1 and wp#/sio2 is high, the wren instruction may set the wel bit can change the values of srwd, bp3, bp2, bp1, bp0. the protected area, which is defned by bp3, bp2, bp1, bp0, is at software pro - tected mode (spm) note: if srwd bit=1 but wp#/sio2 is low, it is impossible to write the status register even if the wel bit has previously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when srwd bit=1, and then wp#/sio2 is low (or wp#/sio2 is low before srwd bit=1), it enters the hardware protected mode (hpm). the data of the protected area is protected by software protected mode by bp3, bp2, bp1, bp0 and hardware protected mode by the wp#/sio2 to against data modifcation. note: to exit the hardware protected mode requires wp#/sio2 driving high once the hardware protected mode is entered. if the wp#/sio2 pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via bp3, bp2, bp1, bp0. if the system enter qpi or set qe=1, the feature of hpm will be disabled. table 7. protection modes note: 1. as defned by the values in the block protect (bp3, bp2, bp1, bp0) bits of the status register, as shown in "table 2. protected area sizes" . mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp3 bits can be changed wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be program or erase. hardware protection mode (hpm) the srwd, bp0-bp3 of status register bits cannot be changed wp#=0, srwd bit=1 the protected area cannot be program or erase. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
34 figure 22. wrsr fow wr en co mm and wr sr co mm and write status register data rdsr command wrsr successfully yes yes wrsr fail no start verify ok? wip=0? no rds r command yes wel=1? no rds r command read w el=0, bp[3:0] , q e, and srwd data rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
35 figure 23. wp# setup timing and hold timing during wrsr when srwd=1 high-z 01h 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so note: wp# must be kept high until the embedded operation fnish. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
36 9-9. read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes lowsending read instruction code 3-byte address on si data out on soto end read operation can use cs# to high at any time during data out. figure 24. read data bytes (read) sequence (spi mode only) sclk si cs# so 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 7654 3 1 7 0 data out 1 0 msb msb 2 39 data out 2 03h high-z command mode 3 mode 0 24-bit address rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
37 9-10. read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. read on spi mode the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si1-dummy byte (default) address on si data out on so to end fast_ read operation can use cs# to high at any time during data out. read on qpi mode the sequence of issuing fast_read instruction in qpi mode is: cs# goes low sending fast_read instruction, 2 cycles 24-bit address interleave on sio3, sio2, sio1 & sio04 dummy cyclesdata out interleave on sio3, sio2, sio1 & sio0 to end qpi fast_read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
38 figure 25. read at higher speed (fast_read) sequence (spi mode) 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 0bh command mode 3 mode 0 24-bit address figure 26. read at higher speed (fast_read) sequence (qpi mode) sclk sio(3:0) cs# a5 a4 a3 a2 a1 a0 x x msb lsb msb lsb data out 1 data out 2 data in 0bh x x h0 l0 h1 l1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 command mode 3 mode 0 24-bit address rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
39 9-11. dual read mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the following data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing dread instruction is: cs# goes low sending dread instruction 3-byte address on si 8-bit dummy cycle data out interleave on so1 & so0 to end dread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. figure 27. dual read mode sequence (command 3b) high impedance 21 345678 0 sclk si/sio0 so/sio1 cs# 9 30 31 32 39 40 41 43 44 45 42 3b d4 d5 d2 d3 d7 d6 d6 d4 d0 d7 d5 d1 command 24 add cycle 8 dummy cycle a23 a22 a1 a0 data out 1 data out 2 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
40 9-12. 2 x i/o read mode (2read) the 2read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits (interleave on 2 i/o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single 2read instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing 2read instruc - tion, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit. the sequence of issuing 2read instruction is: cs# goes low sending 2read instruction 24-bit address inter - leave on sio1 & sio0 4 dummy cycles on sio1 & sio0 data out interleave on sio1 & sio0 to end 2read operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, 2read instruction is rejected without any impact on the program/erase/write status register current cycle. figure 28. 2 x i/o read mode sequence (spi mode only) 21 345678 0 sclk si/sio0 so/sio1 cs# 9 10 17 18 19 20 bbh 21 22 23 24 25 26 27 28 29 30 command 4 dummy cycle mode 3 mode 0 mode 3 mode 0 12 add cycles a23 a21 a19 a5 a3 a1 a4 a2 a a22 a20 a18 d6 d4 d7 d5 data out 1 data out 2 d2 d0 d3 d1 d0 d1 d6 d4 d7 d5 d2 d3 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
41 9-13. quad read mode (qread) the qread instruction enable quad throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single qread instruction. the address counter rolls over to 0 when the highest address has been reached. once writ - ing qread instruction, the following data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing qread instruction is: cs# goes low sending qread instruction 3-byte address on si 8-bit dummy cycle data out interleave on so3, so2, so1 & so0 to end qread operation can use cs# to high at any time during data out. while program/erase/write status register cycle is in progress, qread instruction is rejected without any im - pact on the program/erase/write status register current cycle. figure 29. quad read mode sequence (command 6b) high impedance 21 345678 0 sclk si/so0 so/so1 cs# 29 9 30 31 32 33 38 39 40 41 42 6b high impedance so2 high impedance so3 8 dummy cycles d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d5 d6 d7 a23 a22 a2 a1 a0 command 24 add cycles data out 1 data out 2 data out 3 ? ? ? rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
42 9-14. 4 x i/o read mode (4read) the 4read instruction enable quad throughput of serial flash in read mode. a quad enable (qe) bit of status reg - ister must be set to "1" before sending the 4read instruction. the address is latched on rising edge of sclk, and data of every four bits (interleave on 4 i/o pins) shift out on the falling edge of sclk at a maximum frequency fq. the frst address byte can be at any location. the address is automatically increased to the next higher address af - ter each byte data is shifted out, so the whole memory can be read out at a single 4read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing 4read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. 4 x i/o read on spi mode (4read) the sequence of issuing 4read instruction is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out inter - leave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. 4 x i/o read on qpi mode (4read) the 4read instruction also support on qpi command mode. the sequence of issuing 4read instruction qpi mode is: cs# goes low sending 4read instruction 24-bit address interleave on sio3, sio2, sio1 & sio0 2+4 dummy cycles data out interleave on sio3, sio2, sio1 & sio0 to end 4read operation can use cs# to high at any time during data out. another sequence of issuing 4 read instruction especially useful in random access is : cs# goes low sending 4 read instruction 3-bytes address interleave on sio3, sio2, sio1 & sio0 performance enhance toggling bit p[7:0] 4 dummy cycles data out still cs# goes high cs# goes low (reduce 4 read instruction) 24-bit ran- dom access address. in the performance-enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0]=a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next 4read instruction. once p[7:4] is no longer toggling with p[3:0]; like - wise p[7:0]=ffh,00h,aah or 55h and afterwards cs# is raised and then lowered, the system then will escape from performance enhance mode and return to normal operation. while program/erase/write status register cycle is in progress, 4read instruction is rejected without any impact on the program/erase/write status register current cycle. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
43 figure 30. 4 x i/o read mode sequence (spi mode) 21 345678 0 sclk sio0 sio1 sio2 sio3 cs# 9 1210 11 13 14 ebh p4 p0 p5 p1 p6 p2 p7 p3 15 16 17 18 19 20 21 22 23 24 command 4 dummy cycles performance enhance indicator (note) mode 3 mode 0 6 add cycles a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 d4 d0 d5 d1 data out 1 data out 2 data out 3 d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 note: 1. hi-impedance is inhibited for the two clock cycles. 2. p7p3, p6p2, p5p1 & p4p0 (toggling) is inhibited. figure 31. 4 x i/o read mode sequence (qpi mode) 3 edom sclk sio[3:0] cs# mode 3 a5 a4 a3 a2 a1 a0 x x mode 0 mode 0 msb data out eb h0 l0 h1 l1 h2 l2 h3 l3 x x x x 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 data in 24-bit address rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
44 figure 32. w4read (quad read with 4 dummy cycles) sequence 21 345678 9 10 11 12 13 14 15 command mode 3 mode 16 17 18 20 21 22 23 19 sclk sio0 cs# d4 d0 d5 d1 d6 d2 d7 d3 a9 a8 a10 a11 a5 a4 a6 a7 a1 a0 a2 a3 a13 a12 a14 a15 a17 a16 a18 a19 a21 a20 a22 a23 sio1 sio2 sio3 4 dummy cycles data out 1 data out 2 data out 3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d4 d5 d6 d7d3 6 add cycles e7h rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
45 9-15. burst read this device supports burst read in both spi and qpi mode. to set the burst length, following command operation is required issuing command: c0h in the frst byte (8-clocks), following 4 clocks defning wrap around enable with 0h and disable with1h. next 4 clocks is to defne wrap around depth. defnition as following table: the wrap around unit is defned within the 256byte page, with random initial address. its defned as wrap-around mode disable for the default state of the device. to exit wrap around, it is required to issue another c0 command in which data=1xh. otherwise, wrap around status will be retained until power down or reset command. to change wrap around depth, it is requried to issue another c0 command in which data=0xh. qpi 0bh ebh and spi ebh e7h support wrap around feature after wrap around enable. burst read is supported in both spi and qpi mode. the device id default without burst read. data wrap around wrap depth 00h yes 8-byte 01h yes 16-byte 02h yes 32-byte 03h yes 64-byte 1xh no x 0 cs# sclk sio c0h d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 6 7 8 9 10 1 12 13 14 15 5 mode 3 mode 0 figure 33. spi mode figure 34. qpi mode 0 cs# sclk sio[3:0] h0 msb lsb l0 c0h 1 2 3 mode 3 mode 0 note: msb=most signifcant bit lsb=least signifcant bit rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
46 9-16. performance enhance mode the device could waive the command cycle bits if the two cycle bits after address cycle toggles. performance enhance mode is supported in both spi and qpi mode. in qpi mode, ebh 0bh and spi ebh e7h commands support enhance mode. the performance enhance mode is not supported in dual i/o mode. after entering enhance mode, following cs# go high, the device will stay in the read mode and treat cs# go low of the frst clock as address instead of command cycle. to exit enhance mode, a new fast read command whose frst two dummy cycles is not toggle then exit. or issue ffh command to exit enhance mode. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
47 figure 35. 4 x i/o read enhance performance mode sequence (spi mode) 21 345678 0 sclk sio0 sio1 cs# 9 1210 11 13 14 ebh 15 16 n+1 ........... ...... ........... ........... n+7 n+9 n+13 17 18 19 20 21 22 n sio2 sio3 sio0 sio1 sio2 sio3 performance enhance indicator (note) sclk cs# performance enhance indicator (note) mode 3 mode 0 a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 p4 p0 p5 p1 p6 p2 p7 p3 a21 a17 a13 a9 a5 a1 a8 a4 a a20 a16 a12 a23 a19 a15 a11 a7 a3 a10 a6 a2 a22 a18 a14 p4 p0 p5 p1 p6 p2 p7 p3 command 4 dummy cycles 4 dummy cycles 6 add cycles 6 add cycles d4 d0 d5 d1 data out 1 data out 2 data out n d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 d4 d0 d5 d1 data out 1 data out 2 data out n d4 d0 d5 d1 d4 d0 d5 d1 d6 d2 d7 d3 d6 d2 d7 d3 d6 d2 d7 d3 mode 3 mode 0 note: 1. performance enhance mode, if p7p3 & p6p2 & p5p1 & p4p0 (toggling), ex: a5, 5a, 0f, if not using performance enhance recommend to keep 1 or 0 in performance enhance indicator. 2. reset the performance enhance mode, if p7=p3 or p6=p2 or p5=p1 or p4=p0, ex: aa, 00, ff rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
48 figure 36. 4 x i/o read enhance performance mode sequence (qpi mode) sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 data out data in ebh x p(7:4) p(3:0) x x x h0 l0 h1 l1 4 dummy cycles performance enhance indicator sclk sio[3:0] cs# a5 a4 a3 a2 a1 a0 data out msb lsb msb lsb msb lsb msb lsb x p(7:4) p(3:0) x x x h0 l0 h1 l1 4 dummy cycles performance enhance indicator n+1 ............. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 mode 3 mode 0 mode 0 6 address cycles rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
49 9-17. performance enhance mode reset to conduct the performance enhance mode reset operation in spi mode, ffh command code, 8 clocks, should be issued in 1i/o sequence. in qpi mode, ffffffffh command code, 8 clocks, in 4i/o should be issued. if the system controller is being reset during operation, the fash device will return to the standard spi operation. upon reset of main chip, spi instruction would be issued from the system. instructions like read id (9fh) or fast read (0bh) would be issued. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. figure 37. performance enhance mode reset for fast read quad i/o (spi mode) 21 34567 mode 3 don?t care don?t care don?t care mode mode 3 mode sclk sio0 cs# sio1 ffh sio2 sio3 mode bit reset for quad i/o figure 38. performance enhance mode reset for fast read quad i/o (qpi mode) 21 34567 mode 3 mode mode 3 mode sclk sio[3:0] cs# ffffffffh mode bit reset for quad i/o rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
50 figure 39. sector erase (se) sequence (spi mode) 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20h command mode 3 mode 0 24-bit address figure 40. sector erase (se) sequence (qpi mode) sclk sio[3:0] cs# 20h 2 3 5 7 10 a5 a4 msb lsb 4 a3 a2 6 a1 a0 command mode 3 mode 0 24-bit address 9-18. sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". the instruction is used for any 4k-byte sector. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see "table 4. memory organization" ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the sector is protected by bp3, bp2, bp1, bp0 bits, the sector erase (se) instruction will not be executed on the sector. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
51 9-19. block erase (be32k) the block erase (be32k) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 32k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be32k). any address of the block (see "table 4. memory organization" ) is a valid address for block erase (be32k) instruction. the cs# must go high exactly at the byte boundary (the lat - est eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be32k instruction is: cs# goes low sending be32k instruction code 3-byte address on sics# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the self-timed block erase cycle time (tbe32k) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the block erase cycle is in progress. the wip sets 1 during the tbe32k timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (be32k) instruction will not be executed on the block. figure 41. block erase 32kb (be32k) sequence (spi mode) 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52h command mode 3 mode 0 24-bit address figure 42. block erase 32kb (be32k) sequence (qpi mode) sclk sio[3:0] cs# 52h 2 3 5 7 10 a5 a4 msb 4 a3 a2 6 a1 a0 command mode 3 mode 0 24-bit address rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
52 9-20. block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". the instruction is used for 64k-byte block erase operation. a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block ( please refer to "table 4. memory organization" ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the block erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when block erase cycle is completed, and the write enable latch (wel) bit is reset. if the block is protected by bp3, bp2, bp1, bp0 bits, the block erase (be) instruction will not be executed on the block. figure 43. block erase (be) sequence (spi mode) 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si d8h command mode 3 mode 0 24-bit address figure 44. block erase (be) sequence (qpi mode) sclk sio[3:0] cs# d8h 2 3 10 a5 a4 msb 4 5 a3 a2 6 7 a1 a0 command mode 3 mode 0 24-bit address rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
53 9-21. chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not executed. the sequence of issuing ce instruction is: cs# goes lowsending ce instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp3, bp2, bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only execut - ed when bp3, bp2, bp1, bp0 all set to "0". figure 45. chip erase (ce) sequence (spi mode) 21 34567 0 60h or c7h sclk si cs# command mode 3 mode 0 figure 46. chip erase (ce) sequence (qpi mode) sclk sio[3:0] cs# 60h or c7h 0 1 command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
54 9-22. page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must be executed to set the write enable latch (wel) bit before sending the page program (pp). the device programs only the last 256 data bytes sent to the device. the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. the cs# must be kept low during the whole page program cycle; the cs# must go high exactly at the byte boundary (the latest eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp3, bp2, bp1, bp0 bits, the page program (pp) instruction will not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
55 figure 47. page program (pp) sequence (spi mode) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02h command mode 3 mode 0 24-bit address figure 48. page program (pp) sequence (qpi mode) 210 sclk sio[3:0] cs# data byte 2 data in 02h a5 a4 a3 a2 a1 a0 h0 l0 h1 l1 h2 l2 h3 l3 h255 l255 data byte 1 data byte 3 data byte 4 data byte 256 command mode 3 mode 0 24-bit address rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
56 9-23. 4 x i/o page program (4pp) the quad page program (4pp) instruction is for programming the memory to be "0". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit and quad enable (qe) bit must be set to "1" before sending the quad page program (4pp). the quad page programming takes four pins: sio0, sio1, sio2, and sio3 as address and data input, which can improve programmer performance and the effectiveness of application. the 4pp operation frequency supports as fast as 104mhz. the other function descriptions are as same as standard page program. the sequence of issuing 4pp instruction is: cs# goes low sending 4pp instruction code 3-byte address on sio[3:0] at least 1-byte on data on sio[3:0]cs# goes high. figure 49. 4 x i/o page program (4pp) sequence (spi mode only) a20 a21 a17 a16 a12 a8 a4 a0 a13 a9 a5 a1 d4 d0 d5 d1 21 3456789 6 add cycles data byte 1 data byte 2 data byte 3 data byte 4 0 a22 a18 a14 a10 a6 a2 a23 a19 a15 a11 a7 a3 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 d4 d0 d5 d1 d6 d2 d7 d3 sclk cs# sio0 sio1 sio3 sio2 38h command 10 11 12 13 14 15 16 17 18 19 20 21 mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
57 9-24. deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not ac - tive and all write/program/erase instruction are ignored. when cs# goes high, it's only in deep power-down mode not standby mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes lowsending dp instruction codecs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. once the dp instruction is set, all instructions will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction and softreset command. (those instructions allow the id be - ing reading out). when power-down, or software reset command the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for dp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not be executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode. figure 50. deep power-down (dp) sequence (spi mode) 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9h command mode 3 mode 0 figure 51. deep power-down (dp) sequence (qpi mode) sclk sio[3:0] cs# b9h 0 1 t dp deep power-down mode stand-by mode command mode 3 mode 0 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
58 9-25. enter secured otp (enso) the enso instruction is for entering the additional 4k-bit secured otp mode. the additional 4k-bit secured otp is independent from main array, which may use to store unique serial number for system identifer. after entering the secured otp mode, and then follow standard read or program procedure to read out the data or update data. the secured otp data cannot be updated again once it is lock-down. the sequence of issuing enso instruction is: cs# goes low sending enso instruction to enter secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. please note that wrsr/wrscur commands are not acceptable during the access of secure otp region, once se - curity otp is lock down, only read related commands are valid. 9-26. exit secured otp (exso) the exso instruction is for exiting the additional 4k-bit secured otp mode. the sequence of issuing exso instruction is: cs# goes low sending exso instruction to exit secured otp mode cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. 9-27. read security register (rdscur) the rdscur instruction is for reading the value of security register bits. the read security register can be read at any time (even in program/erase/write status register/write security register condition) and continuously. the sequence of issuing rdscur instruction is : cs# goes lowsending rdscur instructionsecurity register data out on so cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the defnition of the security register bits is as below: secured otp indicator bit. the secured otp indicator bit shows the chip is locked by factory before ex- factory or not. when it is "0", it indicates non-factory lock; "1" indicates factory-lock. lock-down secured otp (ldso) bit. by writing wrscur instruction, the ldso bit may be set to "1" for cus - tomer lock-down purpose. however, once the bit is set to "1" (lock-down), the ldso bit and the 4k-bit secured otp area cannot be update any more. while it is in 4k-bit secured otp mode, main array access is not allowed. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
59 9-28. write security register (wrscur) the wrscur instruction is for changing the values of security register bits. the wren (write enable) instruction is required before issuing wrscur instruction. the wrscur instruction may change the values of bit1 (ldso bit) for customer to lock-down the 4k-bit secured otp area. once the ldso bit is set to "1", the secured otp area cannot be updated any more. the sequence of issuing wrscur instruction is :cs# goes low sending wrscur instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the cs# must go high exactly at the boundary; otherwise, the instruction will be rejected and not executed. bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 wpsel e_fail p_fail reserved esb (erase suspend bit) psb (program suspend bit) ldso (indicate if lock-down) secured otp indicator bit 0=normal wp mode 1=individual mode (default=0) 0=normal erase succeed 1=indicate erase failed (default=0) 0=normal program succeed 1=indicate program failed (default=0) - 0=erase is not suspended 1= erase suspended (default=0) 0=program is not suspended 1= program suspended (default=0) 0 = not lock- down 1 = lock-down (cannot program/ erase otp) 0 = non- factory lock 1 = factory lock non-volatile bit (otp) volatile bit volatile bit volatile bit volatile bit volatile bit non-volatile bit (otp) non-volatile bit (otp) table 8. security register defnition rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
60 9-29. write protection selection (wpsel) there are two write protection methods, (1) bp protection mode (2) individual block protection mode. if wpsel=0, fash is under bp protection mode . if wpsel=1, fash is under individual block protection mode. the default value of wpsel is 0. wpsel command can be used to set wpsel=1. please note that wpsel is an otp bit. once wpsel is set to 1, there is no chance to recover wpsel bit back to 0. if the fash is under bp mode, the indi - vidual block protection mode is disabled. contrarily, if fash is on the individual block protection mode, the bp mode is disabled. every time after the system is powered-on, and the security register bit 7 is checked to be wpsel=1, all the blocks or sectors will be write protected by default. user may only unlock the blocks or sectors via sbulk and gbulk instruction. program or erase functions can only be operated after the unlock instruction is conducted. bp protection mode, wpsel=0: array is protected by bp3~bp0 and bp3~bp0 bits are protected by srwd=1 and wp#=0, where srwd is bit 7 of status register that can be set by wrsr command. individual block protection mode, wpsel=1: blocks are individually protected by their own sram lock bits which are set to 1 after power up. sbulk and sblk command can set sram lock bit to 0 and 1. when the system accepts and executes wpsel instruction, the bit 7 in security register will be set. it will activate sblk, sbulk, rdblock, gblk, gbulk etc instructions to conduct block lock protection and replace the original software protect mode (spm) use (bp3~bp0) indicated block meth - ods.under the individual block protection mode (wpsel=1), hardware protection is performed by driving wp#=0. once wp#=0 all array blocks/sectors are protected regardless of the contents of sram lock bits. the sequence of issuing wpsel instruction is: cs# goes low sending wpsel instruction to enter the individual block protect mode cs# goes high. wpsel instruction function fow is as follows: 64kb 64kb . . . 64kb 64kb bp3 bp2 bp1 bp0 srwd w p# pin bp and srwd if wpsel=0 (1) bp3~bp0 is used to defne the protection group region. (the protected area size see "table 2. protected area sizes") (2) srwd=1 and wp#=0 is used to protect bp3~bp0. in this case, srwd and bp3~bp0 of status register bits can not be changed by wrsr rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
61 the individual block lock mode is effective after setting wpsel=1 64kb 4kb 64kb 4kb sram sram sram 4kb 4kb sram uniform 64kb bl oc ks sram sram 4kb sram sbulk / sblk / gbulk / gblk / rdblock ?? ? ? ? ? ? ? bottom 4kbx16 sectors top 4kbx16 sectors ? power-up: all sram bits=1 (all blocks are default protected). all array cannot be programmed/erased ? sblk/sbulk(36h/39h): - sblk(36h): set sram bit=1 (protect) : array can not be programmed/erased - sbulk(39h): set sram bit=0 (unprotect): array can be programmed/erased - all top 4kbx16 sectors and bottom 4kbx16 sectors and other 64kb uniform blocks can be protected and unprotected by sram bits individually by sblk/sbulk command set. ? gblk/gbulk(7eh/98h): - gblk(7eh): set all sram bits=1,whole chip is protected and cannot be programmed/erased. - gbulk(98h): set all sram bits=0,whole chip is unprotected and can be programmed/erased. - all sectors and blocks sram bits of whole chip can be protected and unprotected at one time by gblk/gbulk command set. ? rdblock(3ch): - use rdblock mode to check the sram bits status after sbulk /sblk/gbulk/gblk command set. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
62 figure 52. wpsel flow rdscur(2bh) command rdsr command rdscur(2bh) command wpsel set successfully yes yes wpsel set fail no start wpsel=1? wip=0? no wpsel disable, block protected by bp[3:0] yes no wren command wpsel=1? wpsel(68h) command wpsel enable. block protected by individual lock (sblk, sbulk, ? etc). rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
63 figure 53. block lock flow rdscur(2bh) command start wren command sblk command ( 36h + 24bit address ) rdsr command rdblock command ( 3ch + 24bit address ) block lock successfully yes yes block lock fail no data = ffh ? wip=0? lock another block? block lock completed no yes no no yes wpsel=1? wpsel command 9-30. single block lock/unlock protection (sblk/sbulk) these instructions are only effective after wpsel was executed. the sblk instruction is for write protection a spec - ifed block (or sector) of memory, using a max -a16 or (a max -a12) address bits to assign a 64kbyte block (or 4k bytes sector) to be protected as read only. the sbulk instruction will cancel the block (or sector) write protection state. this feature allows user to stop protecting the entire block (or sector) through the chip unprotect command (gbulk). the wren (write enable) instruction is required before issuing sblk/sbulk instruction. the sequence of issuing sblk/sbulk instruction is: cs# goes low send sblk/sbulk (36h/39h) instructionsend 3-byte address assign one block (or sector) to be protected on si pin cs# goes high. the cs# must go high exactly at the byte boundary, otherwise the instruction will be rejected and not be executed. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. sblk/sbulk instruction function fow is as follows: rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
64 figure 54. block unlock flow wren command rdscur(2bh) command sbulk command ( 39h + 24bit address ) rdsr command yes rdblock command to verify ( 3ch + 24bit address ) wip=0? unlock another block? yes no block unlock successfully no block unlock fail yes data = ff ? no yes unlock block completed? start wpsel=1? wpsel command rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
65 9-31. read block lock status (rdblock) this instruction is only effective after wpsel was executed. the rdblock instruction is for reading the status of protection lock of a specifed block (or sector), using a max -a16 (or a max -a12) address bits to assign a 64k bytes block (4k bytes sector) and read protection lock status bit which the frst byte of read-out cycle. the status bit is"1" to indicate that this block has be protected, that user can read only but cannot write/program /erase this block. the status bit is "0" to indicate that this block hasn't be protected, and user can read and write this block. the sequence of issuing rdblock instruction is: cs# goes low send rdblock (3ch) instruction send 3-byte address to assign one block on si pin read block's protection lock status bit on so pin cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. 9-32. gang block lock/unlock (gblk/gbulk) these instructions are only effective after wpsel was executed. the gblk/gbulk instruction is for enable/disable the lock protection block of the whole chip. the wren (write enable) instruction is required before issuing gblk/gbulk instruction. the sequence of issuing gblk/gbulk instruction is: cs# goes low send gblk/gbulk (7eh/98h) instruction cs# goes high. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. the cs# must go high exactly at the byte boundary, otherwise, the instruction will be rejected and not be executed. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
66 9-33. program/ erase suspend/ resume the device allow the interruption of sector-erase, block-erase or page-program operations and conduct other operations. details as follows. to enter the suspend/ resume mode: issuing b0h for suspend; 30h for resume (spi/qpi all acceptable) read security register bit2 (psb) and bit3 (esb) (please refer to "table 8. security register defnition" ) to check suspend ready information. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note "figure 55. suspend to read/program latency" , "figure 56. resume to read latency" and "figure 57. resume to suspend latency". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. 9-34. erase suspend erase suspend allows the interruption of all erase operations. after erase suspend, wel bit will be clear, following commands can be accepted. (including: 03h, 0bh, 3bh, 6bh, bbh, ebh, 5ah, c0h, 06h, 04h, 2bh, 9fh, afh, 05h, abh, 90h, 02h, 38h, b1h, c1h, b0h, 30h, 66h, 99h, 00h, 35h, f5h) after issuing erase suspend command, latency time is needed before issuing another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note "figure 55. suspend to read/program latency" , "figure 56. resume to read latency" and "figure 57. resume to suspend latency". esb bit (erase suspend bit) indicates the status of erase suspend operation. esb bit is set to "1" when suspend command is issued during erase operation. when erase operation resumes, esb bit is reset to "0". both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. when esb bit is issued, the write enable latch (wel) bit will be reset. 9-35. program suspend program suspend allows the interruption of all program operations. after program suspend, wel bit will be cleared, only read related, resume and reset command can be accepted. (including: 03h, 0bh, bbh, ebh, e7h, 9fh, afh, 90h, 05h, 2bh, b1h, c1h, 5ah, 3ch, 30h, 66h, 99h, c0h, 35h, f5h, 00h, abh ) after issuing program suspend command, latency time is needed before issuing another command. for "suspend to read", "resume to read", "resume to suspend" timing specifcation please note "figure 55. suspend to read/program latency" , "figure 56. resume to read latency" and "figure 57. resume to suspend latency". psb bit (program suspend bit) indicates the status of program suspend operation. psb bit is set to "1" when suspend command is issued during program operation. when program operation resumes, psb bit is reset to "0". rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
67 figure 55. suspend to read/program latency cs# program latency : 20us erase latency:20us suspend command [b0] read/program command note: please note that program command only available after the erase/suspend operation figure 56. resume to read latency cs# tse/tbe/tpp resume command [30] read command figure 57. resume to suspend latency cs# 1ms resume command [30] suspend command [b0] rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
68 9-36. write-resume the write operation is being resumed when write-resume instruction issued. esb or psb (suspend status bit) in status register will be changed back to 0 the operation of write-resume is as follows: cs# drives low send write resume command cycle (30h) drive cs# high. by polling busy bit in status register, the internal write operation status could be checked to be completed or not. the user may also wait the time lag of tse, tbe, tpp for sector-erase, block-erase or page-programming. wren (command "06" is not required to issue before resume. resume to another suspend operation requires latency time of 1ms. please note that, if "performance enhance mode" is executed during suspend operation, the device can not be resumed. to restart the write command, disable the "performance enhance mode" is required. after the "performance enhance mode" is disable, the write-resume command is effective. 9-37. no operation (nop) the "no operation" command is only able to terminate the reset enable (rsten) command and will not affect any other command. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are don't care when during spi mode. 9-38. software reset (reset-enable (rsten) and reset (rst)) the software reset operation combines two instructions: reset-enable (rsten) command and reset (rst) command. it returns the device to a standby mode. all the volatile bits and settings will be cleared then, which makes the device return to the default status as power on. to execute reset command (rst), the reset-enable (rsten) command must be executed frst to perform the reset operation. if there is any other command to interrupt after the reset-enable command, the reset-enable will be invalid. both spi (8 clocks) and qpi (2 clocks) command cycle can accept by this instruction. the sio[3:1] are "don't care" in spi mode. if the reset command is executed during program or erase operation, the operation will be disabled, the data under processing could be damaged or lost. the reset time is different depending on the last operation. longer latency time is required to recover from a pro - gram operation than from other operations. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
69 figure 58. software reset recovery cs# mode 66 99 stand-by mode trcr trcp trce trcr: 20us (recovery time from read) trcp: 20us (recovery time from program) trce: 12ms (recovery time from erase) figure 59. reset sequence (spi mode) cs# sclk sio0 66h mode 3 mode 0 mode 3 mode 0 99h command command tshsl figure 60. reset sequence (qpi mode) mode 3 sclk sio[3:0] cs# mode 3 99h 66h mode 0 mode 3 mode 0 mode 0 tshsl command command rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
70 9-39. read sfdp mode (rdsfdp) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial fash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. the concept is similar to the one found in the introduction of jedec standard, jesd68 on cfi. the sequence of issuing rdsfdp instruction is same as fast_read: cs# goes lowsend rdsfdp instruction (5ah)send 3 address bytes on si pinsend 1 dummy byte on si pinread sfdp code on soto end rdsfdp operation can use cs# to high at any time during data out. sfdp is a jedec standard, jesd216. figure 61. read serial flash discoverable parameter (rdsfdp) sequence 23 21 345678 9 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 data out 1 dummy cycle msb 7 6543210 data out 2 msb msb 7 47 76543 2 0 1 35 sclk si cs# so sclk si cs# so 5ah command rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
71 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) sfdp signature fixed: 50444653h 00h 07:00 53h 53h 01h 15:08 46h 46h 02h 23:16 44h 44h 03h 31:24 50h 50h sfdp minor revision number start from 00h 04h 07:00 00h 00h sfdp major revision number start from 01h 05h 15:08 01h 01h number of parameter headers this number is 0-based. therefore, 0 indicates 1 parameter header. 06h 23:16 01h 01h unused 07h 31:24 ffh ffh id number (jedec) 00h: it indicates a jedec specifed header. 08h 07:00 00h 00h parameter table minor revision number start from 00h 09h 15:08 00h 00h parameter table major revision number start from 01h 0ah 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 0bh 31:24 09h 09h parameter table pointer (ptp) first address of jedec flash parameter table 0ch 07:00 30h 30h 0dh 15:08 00h 00h 0eh 23:16 00h 00h unused 0fh 31:24 ffh ffh id number (macronix manufacturer id) it indicates macronix manufacturer id 10h 07:00 c2h c2h parameter table minor revision number start from 00h 11h 15:08 00h 00h parameter table major revision number start from 01h 12h 23:16 01h 01h parameter table length (in double word) how many dwords in the parameter table 13h 31:24 04h 04h parameter table pointer (ptp) first address of macronix flash parameter table 14h 07:00 60h 60h 15h 15:08 00h 00h 16h 23:16 00h 00h unused 17h 31:24 ffh ffh table 9. signature and parameter identifcation data values rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
72 table 10. parameter table (0): jedec flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) block/sector erase sizes 00: reserved, 01: 4kb erase, 10: reserved, 11: not support 4kb erase 30h 01:00 01b e5h write granularity 0: 1byte, 1: 64byte or larger 02 1b write enable instruction required for writing to volatile status registers 0: not required 1: required 00h to be written to the status register 03 0b write enable opcode select for writing to volatile status registers 0: use 50h opcode, 1: use 06h opcode note: if target fash status register is nonvolatile, then bits 3 and 4 must be set to 00b. 04 0b unused contains 111b and can never be changed 07:05 111b 4kb erase opcode 31h 15:08 20h 20h (1-1-2) fast read (note2) 0=not support 1=support 32h 16 1b f1h address bytes number used in addressing fash array 00: 3byte only, 01: 3 or 4byte, 10: 4byte only, 11: reserved 18:17 00b double transfer rate (dtr) clocking 0=not support 1=support 19 0b (1-2-2) fast read 0=not support 1=support 20 1b (1-4-4) fast read 0=not support 1=support 21 1b (1-1-4) fast read 0=not support 1=support 22 1b unused 23 1b unused 33h 31:24 ffh ffh flash memory density 37h:34h 31:00 03ffffffh (1-4-4) fast read number of wait states (note3) 0 0000b: wait states (dummy clocks) not support 38h 04:00 0 0100b 44h (1-4-4) fast read number of mode bits (note4) 000b: mode bits not support 07:05 010b (1-4-4) fast read opcode 39h 15:08 ebh ebh (1-1-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ah 20:16 0 1000b 08h (1-1-4) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-1-4) fast read opcode 3bh 31:24 6bh 6bh rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
73 description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) (1-1-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3ch 04:00 0 1000b 08h (1-1-2) fast read number of mode bits 000b: mode bits not support 07:05 000b (1-1-2) fast read opcode 3dh 15:08 3bh 3bh (1-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 3eh 20:16 0 0100b 04h (1-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (1-2-2) fast read opcode 3fh 31:24 bbh bbh (2-2-2) fast read 0=not support 1=support 40h 00 0b feh unused 03:01 111b (4-4-4) fast read 0=not support 1=support 04 1b unused 07:05 111b unused 43h:41h 31:08 ffh ffh unused 45h:44h 15:00 ffh ffh (2-2-2) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 46h 20:16 0 0000b 00h (2-2-2) fast read number of mode bits 000b: mode bits not support 23:21 000b (2-2-2) fast read opcode 47h 31:24 ffh ffh unused 49h:48h 15:00 ffh ffh (4-4-4) fast read number of wait states 0 0000b: wait states (dummy clocks) not support 4ah 20:16 0 0100b 44h (4-4-4) fast read number of mode bits 000b: mode bits not support 23:21 010b (4-4-4) fast read opcode 4bh 31:24 ebh ebh sector type 1 size sector/block size = 2^n bytes (note5) 0x00b: this sector type doesn't exist 4ch 07:00 0ch 0ch sector type 1 erase opcode 4dh 15:08 20h 20h sector type 2 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 4eh 23:16 0fh 0fh sector type 2 erase opcode 4fh 31:24 52h 52h sector type 3 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 50h 07:00 10h 10h sector type 3 erase opcode 51h 15:08 d8h d8h sector type 4 size sector/block size = 2^n bytes 0x00b: this sector type doesn't exist 52h 23:16 00h 00h sector type 4 erase opcode 53h 31:24 ffh ffh rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
74 table 11. parameter table (1): macronix flash parameter tables description comment add (h) (byte) dw add (bit) data (h/b) (note1) data (h) vcc supply maximum voltage 2000h=2.000v 2700h=2.700v 3600h=3.600v 61h:60h 07:00 15:08 00h 20h 00h 20h vcc supply minimum voltage 1650h=1.650v 2250h=2.250v 2350h=2.350v 2700h=2.700v 63h:62h 23:16 31:24 50h 16h 50h 16h h/w reset# pin 0=not support 1=support 65h:64h 00 1b f99dh h/w hold# pin 0=not support 1=support 01 0b deep power down mode 0=not support 1=support 02 1b s/w reset 0=not support 1=support 03 1b s/w reset opcode reset enable (66h) should be issued before reset opcode 11:04 1001 1001b (99h) program suspend/resume 0=not support 1=support 12 1b erase suspend/resume 0=not support 1=support 13 1b unused 14 1b wrap-around read mode 0=not support 1=support 15 1b wrap-around read mode opcode 66h 23:16 c0h c0h wrap-around read data length 08h:support 8b wrap-around read 16h:8b&16b 32h:8b&16b&32b 64h:8b&16b&32b&64b 67h 31:24 64h 64h individual block lock 0=not support 1=support 6bh:68h 00 1b c8d9h individual block lock bit (volatile/nonvolatile) 0=volatile 1=nonvolatile 01 0b individual block lock opcode 09:02 0011 0110b (36h) individual block lock volatile protect bit default protect status 0=protect 1=unprotect 10 0b secured otp 0=not support 1=support 11 1b read lock 0=not support 1=support 12 0b permanent lock 0=not support 1=support 13 0b unused 15:14 11b unused 31:16 ffh ffh unused 6fh:6ch 31:00 ffh ffh rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
75 note 1: h/b is hexadecimal or binary . note 2: (x-y-z) means i/o mode nomenclature used to indicate the number of active pins used for the opcode (x), address (y), and data (z). at the present time, the only valid read sfdp instruction modes are: (1-1-1), (2-2-2), and (4-4-4) note 3: wait states is required dummy clock cycles after the address bits or optional mode bits. note 4: mode bits is optional control bits that follow the address bits. these bits are driven by the system controller if they are specifed. (eg,read performance enhance toggling bits) note 5: 4kb=2^0ch,32kb=2^0fh,64kb=2^10h note 6: all unused and undefned area data is blank ffh rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
76 symbol alt. parameter min. typ. max. unit trlrh reset pulse width 1 us trs reset setup time 15 ns trh reset hold time 15 ns trhrl reset recovery time (during instruction decoding) 20 us trcr reset recovery time read 20 us trce erase 12 ms trcp program 20 us reset recovery time (for wrsr operation) 20 us 10. reset driving the reset# pin low for a period of trlrh or longer will reset the device. after reset cycle, the device is at the following states: - standby mode - all the volatile bits such as wel/wip/sram lock bit will return to the default status as power on. if the device is under programming or erasing, driving the rese t# pin low will also terminate the operation and data could be lost. during the resetting cycle, the so data becomes high impedance and the current will be reduced to minimum. figure 62. reset timing trhrl trs trh trlrh sclk reset# cs# table 12. reset timing rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
77 11. power-on state the device is at below states when power-up: - standby mode (please n ote it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level: - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power-up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. when vcc is lower than vwi (por threshold voltage value), the internal logic is reset and the fash device has no response to any command. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the write, erase, and program command should be sent after the below time delay: - tvsl after vcc reached vcc minimum level the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. please refer to the "figure 69. power-up timing" . note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed. (generally around 0.1uf) - at power-down stage, the vcc drops below vwi level, all operations are disable and device has no response to any command. the data corruption might occur during the stage while a write, program, erase cycle is in progress. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
78 12. electrical specifications figure 63. maximum negative overshoot waveform figure 64. maximum positive overshoot waveform 0v -1.0v 20ns vcc+1.0v 2.0v 20ns notice: 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v or -1.0v for period up to 20ns. table 13. absolute maximum ratings rating value ambient operating temperature industrial grade -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to 2.5v table 14. capacitance ta = 25c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
79 figure 65. input test waveforms and measurement level figure 66. output loading ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns device under test cl 25k ohm 25k ohm +1.8v cl=30pf including jig capacitance rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
80 table 15. dc characteristics notes : 1. t ypical values at vcc = 1.8v, t = 25 c. these currents are valid for all product versions (package and speeds). 2. t ypical value is calculated by simulation. symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max, vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max, vout = vcc or gnd isb1 vcc standby current 1 15 50 ua vin = vcc or gnd, cs# = vcc isb2 deep power-down current 1.5 15 ua vin = vcc or gnd, cs# = vcc icc1 vcc read 1 20 ma f=104mhz, (4 x i/o read) sclk=0.1vcc/0.9vcc, so=open 15 ma f=84mhz, sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 20 25 ma program in progress, cs# = vcc icc3 vcc write status register (wrsr) current 10 20 ma program status register in progress, cs#=vcc icc4 vcc sector/block (32k, 64k) erase current (se/be/be32k) 1 18 25 ma erase in progress, cs#=vcc icc5 vcc chip erase current (ce) 1 20 25 ma erase in progress, cs#=vcc vil input low voltage -0.5 0.2vcc v vih input high voltage 0.8vcc vcc+0.4 v vol output low voltage 0.2 v iol = 100ua voh output high voltage vcc-0.2 v ioh = -100ua temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
81 table 16. ac characteristics symbol alt. parameter min. typ. (2) max. unit fsclk fc clock frequency for the following instructions: fast_read, rdsfdp, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr d.c. 104 mhz frsclk fr clock frequency for read instructions (6) 50 mhz ftsclk ft clock frequency for 2read instructions 84 mhz fq clock frequency for 4read instructions (5) 84/104 mhz tch (1) tclh clock high time others (fsclk) 4.5 ns normal read (frsclk) 9 ns tcl (1) tcll clock low time others (fsclk) 4.5 ns normal read (frsclk) 9 ns tclch (2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl (2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 5 ns tchsl cs# not active hold time (relative to sclk) 5 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 3 ns tchsh cs# active hold time (relative to sclk) 2 ns tshch cs# not active setup time (relative to sclk) 3 ns tshsl (3) tcsh cs# deselect time read 5 ns write/erase/program 30 ns tshqz (2) tdis output disable time 8 ns tclqv tv clock low to output valid loading: 30pf/15pf loading: 30pf 8 ns loading: 15pf 6 ns tclqx tho output hold time 0 ns twhsl write protect setup time 10 ns tshwl write protect hold time 10 ns tdp (2) cs# high to deep power-down mode 10 us tres1 (2) cs# high to standby mode without electronic signature read 30 us tres2 (2) cs# high to standby mode with electronic signature read 30 us trcr recovery time from read 20 us trcp recovery time from program 20 us trce recovery time from erase 12 ms tw write status register cycle time 40 ms tbp byte-program 12 30 us tpp page program cycle time 0.5 3 ms tpp (7) page program cycle time (n bytes) 0.008+ (nx0.004) (8) 3 ms tse sector erase cycle time 35 200 ms tbe32 block erase (32kb) cycle time 0.2 1 s tbe block erase (64kb) cycle time 0.35 2 s tce chip erase cycle time 50 75 s temperature = -40 c to 85 c, vcc = 1.65v ~ 2.0v rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
82 notes: 1. tch + tcl must be greater than or equal to 1/ frequency. 2. typical values given for ta=25 c. not 100% tested. 3. only applicable as a constraint for a wrsr instruction when srwd is set at 1. 4. test condition is shown as "figure 65. input test waveforms and measurement level" , "figure 66. output load - ing". 5. when dummy cycle=4 (in both qpi & spi mode), maximum clock rate=84mhz; when dummy cycle=6 (in both qpi & spi mode), maximum clock rate=104mhz. 6. the maximum clock rate=33mhz when reading secured otp area. 7. while programming consecutive bytes, page program instruction provides optimized timings by selecting to pro - gram the whole 256 bytes or only a few bytes between 1~256 bytes. 8. n=how many bytes to program. in the formula, while n=1, byte program time=12us. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
83 notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "table 16. ac characteristics" . symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v 13. operating conditions at device power-up and power-down ac timing illustrated in "figure 67. ac timing at device power-up" and "figure 68. power-down sequence" are for the supply voltages and the control signals at device power-up and power-down. if the timing in the fgures is ig - nored, the device will not operate correctly. during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. figure 67. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
84 figure 68. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
85 13-1. initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). figure 69. power-up timing note: vcc (max.) is 2.0v and vcc (min.) is 1.65v. note: 1. these parameters are characterized only. table 17. power-up timing and vwi threshold v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) v wi symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low (vcc rise time) 800 us vwi(1) command inhibit voltage 1.0 1.4 v rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
86 14. erase and programming performance note: 1. t ypical erase assumes the following conditions: 25 c, 1.8v, and all zero pattern. 2. under worst conditions of 85 c and 1.65v. 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 4. the maximum chip progra mming time is evaluated under the worst conditions of 0 c, vcc=1.8v, and 100k cy - cle with 90% confdence level. 5. t ypical program assumes the following conditions: 25 c, 1.8v, and checkerboard pattern. 15. latch-up characteristics parameter min. typ. (1) max. (2) unit write status register cycle time 40 ms sector erase cycle time (4kb) 35 200 ms block erase cycle time (32kb) 0.2 1 s block erase cycle time (64kb) 0.35 2 s chip erase cycle time 50 75 s byte program time (via page program command) 12 (5) 30 us page program time 0.5 (5) 3 ms erase/program cycle 100,000 cycles min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 1.8v, one pin at a time. rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
87 16. ordering information part no. clock (mhz) temperature package remark mx25U6435Fm2i-10g 104 -40 c~85 c 8-sop (200mil) mx25U6435Fzni-10g 104 -40 c~85 c 8-wson (6x5mm) rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
88 17. part name description mx 25 u 10 zn i g option: g: rohs compliant and halogen-free speed: 10: 104mhz temperature range: i: industrial (-40c to 85c) package: m2: 8-sop(200mil) zn: 8-wson density & mode: 6435f: 64mb type: u: 1.8v device: 25: serial flash 6435f rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
89 18. package information rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
90 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
91 19. revision history revision no. description page date 0.01 1. modifed chip erase cycle time p78,83 aug/25/2011 2. modifed tvsl(min.) from 500us to 800us p82 0.02 1. changed title from "advanced information" to "preliminary" p4 oct/06/2011 2. modifed write protection selection (wpsel) description p59,60 3. modifed power-up timing p84 1.0 1. modifed tvsl(min.) in power-up timing table p84 feb/03/2012 2. modifed valu e of twhsl, tshwl, tchdx, tchsh, tshch, p79,80 tshsl and isb1(max.) in characteristics table 3. added reset# description for write/erase execution p33,49,50~53,58,75 1.1 1. add dread function p7,14,17,39 sep/25/2013 2. add qread function p7,14,17,41 3. update drea d(1-1-2) / qread(1-1-4) in sfdp table p72,73 4. modifed data retention value p4 5. remove mx25u3235f all 6. modifed tvsl value p85 7. modify accepted commands after erase suspend p66 8. modifed pag e program time p4,81,86 1.2 1. updated eras e time and consumption current p4 oct/23/2013 2. updated isb1, isb2, icc3 and icc4 in dc table p80 3. updated tse, tbe32, tbe and tce in ac table p81 4. updated eras e time p86 rev. 1.2, oct. 23, 2013 mx25U6435F p/n: pm1978
mx25U6435F 92 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which have been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2011~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only. for the contact and order information, please visit macronixs web site at: http://www.macronix.com

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